Differential and Higher Order Attacks -- A First-Order DPA Attack Against AES in Counter Mode with Unknown Initial Counter -- Gaussian Mixture Models for Higher-Order Side Channel Analysis -- Side Channel Cryptanalysis of a Higher Order Masking Scheme -- Random Number Generation and Device Identification -- High-Speed True Random Number Generation with Logic Gates Only -- FPGA Intrinsic PUFs and Their Use for IP Protection -- Logic Styles: Masking and Routing -- Evaluation of the Masked Logic Style MDPL on a Prototype Chip -- Masking and Dual-Rail Logic Don’t Add Up -- DPA-Resistance Without Routing Constraints? -- Efficient Algorithms for Embedded Processors -- On the Power of Bitslice Implementation on Intel Core2 Processor -- Highly Regular Right-to-Left Algorithms for Scalar Multiplication -- MAME: A Compression Function with Reduced Hardware Requirements -- Collision Attacks and Fault Analysis -- Collision Attacks on AES-Based MAC: Alpha-MAC -- Secret External Encodings Do Not Prevent Transient Fault Analysis -- Two New Techniques of Side-Channel Cryptanalysis -- High Speed AES Implementations -- AES Encryption Implementation and Analysis on Commodity Graphics Processing Units -- Multi-gigabit GCM-AES Architecture Optimized for FPGAs -- Public-Key Cryptography -- Arithmetic Operators for Pairing-Based Cryptography -- FPGA Design of Self-certified Signature Verification on Koblitz Curves -- How to Maximize the Potential of FPGA Resources for Modular Exponentiation -- Implementation Cost of Countermeasures -- TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks -- Power Analysis Resistant AES Implementation with Instruction Set Extensions -- Security Issues for RF and RFID -- Power and EM Attacks on Passive RFID Devices -- RFID Noisy Reader How to Prevent from Eavesdropping on the Communication? -- RF-DNA: Radio-Frequency Certificates of Authenticity -- Special Purpose Hardware for Cryptanalysis -- CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method -- Collision Search for Elliptic Curve Discrete Logarithm over GF(2 m ) with FPGA -- A Hardware-Assisted Realtime Attack on A5/2 Without Precomputations -- Side Channel Analysis -- Differential Behavioral Analysis -- Information Theoretic Evaluation of Side-Channel Resistant Logic Styles -- Problems and Solutions for Lightweight Devices -- On the Implementation of a Fast Prime Generation Algorithm -- PRESENT: An Ultra-Lightweight Block Cipher -- Cryptographic Hardware and Embedded Systems - CHES 2007.

This book constitutes the refereed proceedings of the 9th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2007, held in Vienna, Austria, September 10-13, 2007. The 31 revised full papers were carefully reviewed and selected from 99 submissions. The papers are organized in topical sections on side channels, low resources, hardware attacks and countermeasures, special purpose hardware, efficient algorithms for embedded processors, side channels, hardware attacks and countermeasures, efficient hardware, trusted computing, side channels, hardware attacks and countermeasures, as well as efficient hardware.